A cell-based IC is a kind of ASIC (Application Specific Integrated Circuit). In other words, this is a semi-custom LSI (Large Scale Integrated) circuit to be designed and manufactured based on combinations of a variety of logic cells prepared as a library.
For example, the cell-based IC may be formed as an integrated circuit including a mixture of basic standard cells and large-scaled circuit blocks (mega cells or macro cells).
The cell-based IC implemented by the standard cells may include random logic.
A cell-based semi-custom design method has been conventionally employed for ASIC design.
This design method combines common intellectual property registered with a library and uses an automatic arrangement wiring tool to improve efficiency of IC design.
However, this design method has a problem of noise due to the compactness and high speed of cell-based ICs.
Specifically, in order to switch logic circuits in a cell-based IC at a high speed, there is a need to charge/discharge load capacitors connected to outputs of the logic circuits at a high speed. As a result, in switching of the logic circuits, very high pulse-like current flows into a power wiring or a ground wiring of the cell-based IC, and power or ground potential is greatly varied due to resistance and inductance of the power wiring or the ground wiring of the cell-based IC. Such potential variation may result in a low switching speed and circuit malfunction.
For the purpose of avoiding this problem, various methods of placing a decoupling capacitor (bypass condenser) between the power and ground wiring have been proposed.
In the related art, a decoupling MOS (Metal Oxide Semiconductor) capacitor cell using a CMOS (Complementary Metal Oxide Semiconductor) transistor has been employed as a decoupling capacitor inserted between the power wiring and the ground wiring. However, the decoupling MOS capacitor cell has its own disadvantage. The fining process may result in the thinness of the gate oxide film, which in turn causes insulation of a gate oxide film to be insufficient. Also, this may cause the increase in leak current and thus the increase in power consumption.
In particular, when using an nMOS transistor for a decoupling capacitor, leak current is about ten times as high as that of a pMOS transistor.